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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:35:27 12/25/2012 
-- Design Name: 
-- Module Name:    rcon - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rcon is
    Port ( clk : in  STD_LOGIC;
           datain : in  STD_LOGIC_VECTOR (7 downto 0);
           dataout : out  STD_LOGIC_VECTOR (7 downto 0));
end rcon;

architecture Behavioral of rcon is

begin
process(clk)
begin 
		if(rising_edge(clk)) then
		case datain is
		when X"01" => dataout <=X"01";
		when X"02" => dataout <=X"02";
		when X"03" => dataout <=X"04";
		when X"04" => dataout <=X"08";
		when X"05" => dataout <=X"10";
		when X"06" => dataout <=X"20";
		when X"07" => dataout <=X"40";
		when X"08" => dataout <=X"80";
		when X"09" => dataout <=X"1b";
		when X"0a" => dataout <=X"36";
		
		when others =>dataout <=(others=>'0');
		end case;
		end if;
end process;
end Behavioral;

